View NCP1031DR2_6343718.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2004 august, 2004 ? rev. 4 1 publication order number: ncp1030/d ncp1030, ncp1031 low power pwm controller with on-chip power switch and startup circuits for 48v telecom systems the ncp1030 and ncp1031 are a family of miniature high?voltage monolithic switching regulators with on?chip power switch and startup circuits. the ncp103x family incorporates in a single ic all the active power, control logic and protection circuitry required to implement, with minimal external components, several switching regulator applications, such as a secondary side bias supply or a low power dc?dc converter. this controller family is ideally suited for 48 v telecom, 42 v automotive and 12 v input applications. the ncp103x can be configured in any single?ended topology such as forward or flyback. the ncp1030 is targeted for applications requiring up to 3 w, and the ncp1031 is targeted for applications requiring up to 6 w. the internal error amplifier allows the ncp103x family to be easily configured for secondary or primary side regulation operation in isolated and non?isolated configurations. the fixed frequency oscillator is optimized for operation up to 1 mhz and is capable of external frequency synchronization, providing additional design flexibility. in addition, the ncp103x incorporates individual line undervoltage and overvoltage detectors, cycle by cycle current limit and thermal shutdown to protect the controller under fault conditions. the preset current limit thresholds eliminate the need for external sensing components. features ? on chip high 200 v power switch circuit and startup circuit ? internal startup regulator with auxiliary winding override ? operation up to 1 mhz ? external frequency synchronization capability ? frequency fold?down under fault conditions ? trimmed 2% internal reference ? line undervoltage and overvoltage detectors ? cycle by cycle current limit using sensefet ? active leb circuit ? overtemperature protection ? internal error amplifier typical applications ? secondary side bias supply for isolated dc?dc converters ? stand alone low power dc?dc converter ? low power bias supply ? low power boost converter http://onsemi.com device package shipping 2 ordering information ncp1030dmr2 micro8 4000/tape & reel NCP1031DR2 so?8 so?8 d suffix case 751 2500/tape & reel marking diagrams 1030/n1031 = specific device code a = assembly location l = wafer lot y = year w = work week micro8 dm suffix case 846a n1031 alyw 1030 ayw 8 1 8 1 1 gnd 2 c t 3 v fb 4 comp v cc v drain ov uv 8 7 6 5 (top view) pin connections 8 1 8 1 2for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d.
ncp1030, ncp1031 http://onsemi.com 2 figure 1. ncp1030/31 functional block diagram thermal shutdown one shot pulse io ? + reset dominant latch s r ? + ? + ? + ? + 7.5 v/10 v 10 v 6.5 v 2.5 v ? + leb reset dominant latch sq r 50 mv ? + ? + ? + ? + 2.5 v ? + internal bias 16 v 10 v 10 v 10 v 10 v gnd vfb comp uv ov disable 3.0 v/3.5 v + ? pwm latch pwm comparator error amplifier current limit comparator v drain r sense 10 v v cc c t i 1 i 2 = 3i 1 q c t ramp ? + ? + 2 k 4.5 v i start functional pin description pin name function description 1 gnd ground ground reference pin for the circuit. 2 c t oscillator frequency selection an external capacitor connected to this pin sets the oscillator frequency up to 1 mhz. the oscillator can be synchronized to a higher frequency by charging or discharging c t to trip the internal 3.0 v/3.5 v comparator. if a fault condition exists, the power switch is disabled and the frequency is reduced by a factor of 7. 3 v fb feedback input the regulated voltage is scaled down to 2.5 v by means of a resistor divider. regulation is achieved by comparing the scaled voltage to an internal 2.5 v reference. 4 comp error amplifier compensation requires external compensation network between comp and v fb pins. this pin is effectively grounded if faults are present. 5 ov line overvoltage shutdown line voltage (v in ) is scaled down using an external resistor divider such that the ov voltage reaches 2.5 v when line voltage reaches its maximum operating voltage. 6 uv line undervoltage shutdown line voltage is scaled down using an external resistor divider such that the uv voltage reaches 2.5 v when line voltage reaches its minimum operating voltage. 7 v cc supply voltage this pin is connected to an external capacitor for energy storage. during turn?on, the startup circuit sources current to charge the capacitor connected to this pin. when the supply voltage reaches v cc(on) , the startup circuit turns off and the power switch is enabled if no faults are present. an external winding is used to supply power after initial startup to reduce power dissipation. v cc should not exceed 16 v. 8 v drain power switch and startup circuits this pin directly connects the power switch and startup circuits to one of the transformer windings. the internal high voltage power switch circuit is connected between this pin and ground. v drain should not exceed 200 v.
ncp1030, ncp1031 http://onsemi.com 3 figure 2. pulse width modulation timing diagram c t ramp c t charge signal pwm comparator output pwm latch output power switch circuit gate drive leading edge blanking output comp voltage current limit propagation delay current limit threshold normal pwm operating range output overload figure 3. auxiliary winding operation with output overload timing diagram v cc(on) v cc(off) v cc(reset) 0 v 0 ma i start 0 v 0 v v drain v fb normal operation power?up & standby operation output overload 2.5 v v uv 0 v 3.0 v
ncp1030, ncp1031 http://onsemi.com 4 maximum ratings rating symbol value unit power switch and startup circuits voltage v drain ?0.3 to 200 v power switch and startup circuits input current ? ncp1030 ? ncp1031 i drain 1.0 2.0 a v cc voltage range v cc ?0.3 to 16 v all other inputs/outputs voltage range v io ?0.3 to 10 v v cc and all other inputs/outputs current i io 100 ma operating junction temperature t j ?40 to 125 c storage temperature t stg ?55 to 150 c power dissipation (t j = 25 c, 2.0 oz., 1.0 sq inch printed circuit copper clad) dm suffix, plastic package case 846a d suffix, plastic package case 751 0.69 0.93 w thermal resistance, junction to air (2.0 oz. printed circuit copper clad) dm suffix, plastic package case 846a 0.36 sq. inch 1.0 sq. inch d suffix, plastic package case 751 0.36 sq. inch 1.0 sq. inch r ja 181 162 135 117 c/w maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. a. this device contains esd protection circuitry and exceeds the following tests: pins 1?7: human body model 2000v per mil?std?883, method 3015. pins 1?7: machine model method 200 v. pin 8 is connected to the high voltage startup and power switch circuits and rated only to the maximum voltage rating of the pa rt, or 200 v. b. this device contains latchup protection and exceeds 100 ma per jedec standard jesd78.
ncp1030, ncp1031 http://onsemi.com 5 dc electrical characteristics (v drain = 48 v, v cc = 12 v, c t = 560 pf, v uv = 3 v, v ov = 2 v, v fb = 2.3 v, v comp = 2.5 v, t j = ?40 c to 125 c, typical values shown are for t j = 25 c unless otherwise noted.) (note 1) characteristics symbol min typ max unit startup control startup circuit output current (v fb = v comp ) ncp1030 t j = 25 c v cc = 0 v v cc = v cc(on) ? 0.2 v t j = ?40 c to 125 c v cc = 0 v v cc = v cc(on) ? 0.2 v ncp1031 t j = 25 c v cc = 0 v v cc = v cc(on) ? 0.2 v t j = ?40 c to 125 c v cc = 0 v v cc = v cc(on) ? 0.2 v i start 10 6.0 8.0 2.0 13 8.0 11 4.0 12.5 8.6 ? ? 16 12 ? ? 15 12 16 13 19 16 21 18 ma v cc supply monitor (v fb = 2.7 v) startup threshold voltage (v cc increasing) minimum operating v cc after turn?on (v cc increasing) hysteresis voltage v cc(on) v cc(off) v cc(hys) 9.6 7.0 ? 10.2 7.6 2.6 10.6 8.0 ? v undervoltage lockout threshold voltage, v cc decreasing (v fb = v comp ) v cc(reset) 6.0 6.6 7.0 v minimum startup voltage (pin 8) i start = 0.5 ma, v cc =v cc(on) ? 0.2 v v start(min) ? 16.8 18.5 v error amplifier reference voltage (v comp = v fb , follower mode) t j = 25 c t j = ?40 c to 125 c v ref 2.45 2.40 2.5 2.5 2.55 2.60 v line regulation (v cc = 8 v to 16 v, t j = 25 c) reg line ? 1.0 5.0 mv input bias current (v fb = 2.3 v) i vfb ? 0.1 1.0 a comp source current i src 80 110 140 a comp sink current (v fb = 2.7 v) i snk 200 550 900 a comp maximum voltage (i src = 0 a) v c(max) 4.5 ? ? v comp minimum voltage (i snk = 0 a, v fb = 2.7 v) v c(min) ? ? 1.0 v open loop voltage gain a vol ? 80 ? db gain bandwidth product gbw ? 1.0 ? mhz line under/overvoltage detector undervoltage lockout (v fb = v comp ) voltage threshold (v in increasing) voltage hysteresis input bias current v uv v uv(hys) i uv 2.400 0.075 ? 2.550 0.175 0 2.700 0.275 1.0 v v a overvoltage lockout (v fb = v comp ) voltage threshold (v in increasing) voltage hysteresis input bias current v ov v ov(hys) i ov 2.400 0.075 ? 2.550 0.175 0 2.700 0.275 1.0 v v a 1. production testing for ncp1030dmr2 is performed at 25 c only; limits at ?40 c and 125 c are guaranteed by design.
ncp1030, ncp1031 http://onsemi.com 6 dc electrical characteristics (v drain = 48 v, v cc = 12 v, c t = 560 pf, v uv = 3 v, v ov = 2 v, v fb = 2.3 v, v comp = 2.5 v, t j = ?40 c to 125 c, typical values shown are for t j = 25 c unless otherwise noted.) (note 2) characteristics symbol min typ max unit oscillator frequency (c t = 560 pf, note 3) t j = 25 c t j = ?40 c to 125 c f osc1 275 260 300 ? 325 325 khz frequency (c t = 100 pf) f osc2 ? 800 ? khz charge current (v ct = 3.25 v) i ct(c) ? 215 ? a discharge current (v ct = 3.25 v) i ct(d) ? 645 ? a oscillator ramp peak valley vrpk v rvly ? ? 3.5 3.0 ? ? v pwm comparator maximum duty cycle dc max 70 75 80 % power switch circuit power switch circuit on?state resistance (i d = 100 ma) ncp1030 t j = 25 c t j = 125 c ncp1031 t j = 25 c t j = 125 c r ds(on) ? ? ? ? 4.1 6.0 2.1 3.5 7.0 12 3.0 6.0 power switch circuit and startup circuit breakdown voltage (i d = 100 a, t j = 25 c) v (br)ds 200 ? ? v power switch circuit and startup circuit off?state leakage current (v drain = 200 v, v uv = 2.0 v) t j = 25 c t j = ?40 to 125 c i ds(off) ? ? 13 ? 25 50 a switching characteristics (v ds = 48 v, r l = 100 ) rise time fall time t r t f ? ? 22 24 ? ? ns current limit and over temperature protection current limit threshold (t j = 25 c) ncp1030 (di/dt = 0.5 a/ s) ncp1031 (di/dt = 1.0 a/ s) i lim 350 700 515 1050 680 1360 ma propagation delay, current limit threshold to power switch circuit output (leading edge blanking plus current limit delay) t plh ? 100 ? ns thermal protection (note 4) shutdown threshold (t j increasing) hysteresis t shdn t hys 125 ? 150 45 ? ? c total device supply current after uv turn?on power switch enabled power switch disabled non?fault condition (v fb = 2.7 v) fault condition (v fb = 2.7 v, v uv = 2.0 v) i cc1 i cc2 i cc3 2.0 ? ? 3.0 1.5 0.65 4.0 2.0 1.2 ma 2. production testing for ncp1030dmr2 is performed at 25 c only; limits at ?40 c and 125 c are guaranteed by design. 3. oscillator frequency can be externally synchronized to the maximum frequency of the device. 4. guaranteed by design only.
ncp1030, ncp1031 http://onsemi.com 7 typical characteristics v cc , supply voltage (v) 13.0 12.5 12.0 11.5 8.0 8.5 9.0 9.5 11.0 10.5 0 10.0 24 6810 i start , startup current (ma) ncp1030 v drain = 48 v t j = 25 c figure 4. ncp1030 startup current vs. supply voltage 20 18 16 14 0 2 4 6 12 10 8 i start , startup current (ma) ncp1030 v drain = 48 v ?50 ?25 0 25 50 150 t j , junction temperature ( c) figure 5. ncp1031 startup current vs. supply voltage 75 100 125 v cc = 0 v v cc = v cc(on) ? 0.2 v v drain , drain voltage (v) 12 10 8 0 2 6 0 4 25 50 75 100 200 i start , startup current (ma) figure 6. ncp1030 startup current vs. junction temperature 125 150 175 t j = 25 c v cc = v cc(on) ? 0.2 v figure 7. ncp1031 startup current vs. junction temperature figure 8. ncp1030 startup current vs. drain voltage figure 9. ncp1031 startup current vs. drain voltage t j = ?40 c t j = 125 c v cc , supply voltage (v) 20 19 18 17 10 11 12 13 16 15 0 14 24 6810 i start , startup current (ma) ncp1031 v drain = 48 v t j = 25 c 20 18 16 14 0 2 4 6 12 10 8 i start , startup current (ma) ncp1031 v drain = 48 v ?50 ?25 0 25 50 150 t j , junction temperature ( c) 75 100 125 v cc = 0 v v cc = v cc(on) ? 0.2 v v drain , drain voltage (v) 12 10 8 0 2 6 0 4 25 50 75 100 200 i start , startup current (ma) 125 150 175 t j = 25 c t j = ?40 c t j = 125 c ncp1030 ncp1031 20 14 18 16 v cc = v cc(on) ? 0.2 v
ncp1030, ncp1031 http://onsemi.com 8 typical characteristics figure 10. supply voltage thresholds vs. junction temperature figure 11. undervoltage lockout threshold vs. junction temperature figure 12. minimum startup voltage vs. junction temperature 11.0 10.5 10.0 9.5 6.0 6.5 7.0 7.5 9.0 8.5 8.0 v cc , supply voltage (v) ?50 ?25 0 50 150 t j , junction temperature ( c) figure 13. reference voltage vs. junction temperature 75 100 125 25 startup threshold minimum operating threshold t j , junction temperature ( c) figure 14. comp source current vs. junction temperature figure 15. comp sink current vs. junction temperature ?50 ?25 0 25 50 15 0 75 100 125 6.80 6.75 6.70 6.65 6.30 6.35 6.40 6.45 6.60 6.55 6.50 v cc(reset) , undervoltage lockout threshold (v) 2.70 2.65 2.60 2.55 2.20 2.25 2.30 2.35 2.50 2.45 2.40 v ref , reference voltage (v) ?25 t j , junction temperature ( c) ?50 0 25 50 75 100 125 150 v cc = 12 v 20.0 19.5 19.0 18.5 15.0 15.5 16.0 16.5 18.0 17.5 17.0 v start(min) , minimum startup voltage (v) ?25 t j , junction temperature ( c) ?50 0 25 50 75 100 125 150 v cc = v cc(on) ? 0.2 v i start = 0.5 ma v cc = 12 v v comp = 2.5 v v fb = 2.3 v 145 140 135 130 95 100 105 110 125 120 115 i src , comp source current ( a) ?25 t j , junction temperature ( c) ?50 0 25 50 75 100 125 150 840 790 740 690 390 440 490 640 590 540 i snk , comp sink current ( a) 340 ?25 t j , junction temperature ( c) ?50 0 25 50 75 100 125 150 v cc = 12 v v comp = 2.5 v v fb = 2.7 v
ncp1030, ncp1031 http://onsemi.com 9 typical characteristics figure 16. line under/overvoltage thresholds vs. junction temperature t j , junction temperature ( c) ?50 ?25 0 50 150 75 100 125 25 2.600 2.575 2.550 2.525 2.350 2.375 2.400 2.425 2.500 2.475 2.450 v uv/ov , line under/overvoltage thresholds (v) 200 190 180 170 120 130 160 150 140 v uv/ov(hys) , under/overvoltage hysteresis (mv) ?25 t j , junction temperature ( c) ?50 0 25 50 75 100 125 150 210 220 figure 17. line under/overvoltage hysteresis vs. junction temperature figure 18. oscillator frequency vs. timing capacitor figure 19. oscillator frequency vs. junction temperature 1000 900 800 700 0 100 200 300 600 500 400 f osc , oscillator frequency (khz) c t , timing capacitor (pf) figure 20. maximum duty cycle vs. junction temperature 0 200 400 600 800 1000 v cc = 12 v t j = 25 c t j , junction temperature ( c) figure 21. power switch circuit on resistance vs. junction temperature v cc = 12 v 1100 1000 900 800 100 200 400 700 600 500 f osc , oscillator frequency (khz) ?50 ?25 0 25 150 50 75 100 125 300 c t = 47 pf c t = 220 pf c t = 1000 pf 77.0 76.5 76.0 75.5 72.0 72.5 73.0 73.5 75.0 74.5 74.0 dc max , maximum duty cycle (%) ?50 ?25 0 25 50 75 t j , junction temperature ( c) 100 125 150 f osc = 1000 khz f osc = 200 khz v cc = 12 v 8 7 6 0 1 2 3 5 4 r ds(on) , power switch circuit on resistance ( ) ?50 ?25 0 25 50 75 t j , junction temperature ( c) 100 125 150 v cc = 12 v i d = 100 ma ncp1030 ncp1031
ncp1030, ncp1031 http://onsemi.com 10 typical characteristics figure 22. power switch circuit output capacitance vs. drain voltage c out , output capacitance (pf) figure 23. power switch circuit and startup circuit leakage current vs. drain voltage 1000 10 100 figure 24. ncp1030 current limit threshold vs. junction temperature 0 40 80 120 160 200 v drain , drain voltage (v) 40 35 30 0 5 10 15 25 20 i ds(off) , power switch and startup circuits leakage current ( a) figure 25. ncp1031 current limit threshold vs. junction temperature 0 50 100 150 v drain , drain voltage (v) 200 250 300 t j = ?40 c t j = 25 c t j = 125 c v cc = 12 v ncp1030 ncp1031 600 575 550 525 350 375 500 475 400 i lim , current limit threshold (ma) t j , junction temperature ( c) ?50 ?25 0 25 50 75 t j = 25 c 100 125 150 425 450 600 575 550 525 350 375 500 475 400 i lim , current limit threshold (ma) current slew rate (ma/ s) 375 400 425 450 475 500 425 450 current slew rate = 500 ma/ s figure 26. ncp1030 current limit threshold vs. current slew rate figure 27. ncp1031 current limit threshold vs. current slew rate 1200 1150 1100 1050 700 750 1000 950 800 i lim , current limit threshold (ma) t j , junction temperature ( c) ?50 ?25 0 25 50 75 t j = 25 c 100 125 150 850 900 1200 1150 1100 1050 700 750 1000 950 800 i lim , current limit threshold (ma) current slew rate (ma/ s) 750 800 850 900 950 1000 850 900 current slew rate = 1 a/ s ncp1030 ncp1030 ncp1031 ncp1031
ncp1030, ncp1031 http://onsemi.com 11 typical characteristics figure 28. operating supply current vs. supply voltage figure 29. supply current vs. junction temperature 4.1 3.9 3.3 2.5 3.1 2.7 i cc1 , operating supply current (ma) v cc , supply voltage (v) figure 30. operating supply current vs. oscillator frequency 10 11 12 13 14 15 16 2.9 v drain = 48 v t j = 25 c c t = 560 pf 4.0 2.5 2.0 0 1.5 0.5 i cc , supply current (ma) t j , junction temperature ( c) ?50 ?25 0 25 50 75 100 1.0 v cc = 12 v c t = 560 pf 125 150 v uv = 3.0 v, v fb = 2.3 v v uv = 3.0 v, v fb = 2.7 v v uv = 2.0 v 3.0 3.7 3.5 3.5 10 7 6 2 5 3 i cc , power supply current (ma) f osc , oscillator frequency (khz) 200 300 400 500 600 700 800 4 900 1000 t j = 25 c 8 9 ncp1030 ncp1031
ncp1030, ncp1031 http://onsemi.com 12 figure 31. secondary side bias supply configuration gnd comp + v in ? v bias gnd secondary side control v cc v drain uv ov c t v fb + v out ? ncp103x figure 32. boost circuit configuration gnd comp v out v cc v drain uv ov c t v fb + v in ? + ? ncp103x v cc v cc
ncp1030, ncp1031 http://onsemi.com 13 operating description introduction the ncp1030 and ncp1031 are a family of miniature monolithic voltage?mode switching regulators designed for isolated and non?isolated bias supply applications. the internal startup circuit and the mosfet are rated at 200 v, making them ideal for 48 v telecom and 42 v automotive applications. in addition, the ncp103x family can operate from an existing 12 v supply. this controller family is optimized for operation up to 1 mhz. the ncp103x family incorporates in a single ic all the active power, control logic and protection circuitry required to implement, with a minimum of external components, several switching regulator applications, such as a secondary side bias supply or a low power dc?dc converter. the ncp1030 is available in the space saving micro8 package and is tar geted for applications requiring up to 3 w. the ncp1031 is targeted for applications up to 6 w and is available in the so?8 package. the ncp103x includes an extensive set of features including over temperature protection, cycle by cycle current limit, individual line under and overvoltage detection comparators with hysteresis, and regulator output undervoltage lockout with hysteresis, providing full protection during fault conditions. a description of each of the functional blocks is given below, and the representative block diagram is shown in figure 2. startup circuit and undervoltage lockout the ncp103x contains an internal 200 v startup regulator that eliminates the need for external startup components. the startup regulator consists of a constant current source that supplies current from the input line (v in ) to the capacitor on the v cc pin (c cc ). once the v cc voltage reaches approximately 10 v, the startup circuit is disabled and the power switch circuit is enabled if no faults are present. during this self?bias mode, power to the ncp103x is supplied by the v cc capacitor. the startup regulator turns on again once v cc reaches 7.5 v. this a7.5?10o mode of operation is known as dynamic self supply (dss). the ncp1030 and ncp1031 startup currents are 12 ma and 16 ma, respectively. if v cc falls below 7.5 v, the device enters a re?start mode. while in the re?start mode, the v cc capacitor is allowed to discharge to 6.5 v while the power switch is enabled. once the 6.5 v threshold is reached, the power switch circuit is disabled and the startup regulator is enabled to charge the v cc capacitor. the power switch is enabled again once the v cc voltage reaches 10 v. therefore, the external v cc capacitor must be sized such that a voltage greater than 7.5 v is maintained on the v cc capacitor while the converter output reaches regulation. otherwise, the converter will enter the re?start mode. equation (1) provides a guideline for the selection of the v cc capacitor for a forward converter; forward: (eq. 1) c cc cos ?1 1 v out n p dc v in n s l out c out i bias 2.6 where, i bias is the bias current supplied by the v cc capacitor including the ic bias current (i cc1 ) and any additional current used to bias the feedback resistors (if used). after initial startup, the v cc pin should be biased above v cc(off) using an auxiliary winding. this will prevent the startup regulator from turning on and reduce power dissipation. also, the load should not be directly connected to the v cc capacitor. otherwise, the load may override the startup circuit. figure 33 shows the recommended configuration for a non?isolated flyback converter. figure 33. non?isolated bias supply configuration gnd comp + v in ? v cc v drain uv ov c t v fb ncp103x + v out ? the maximum voltage rating of the startup circuit is 200 v. power dissipation should be observed to avoid exceeding the maximum power dissipation of the package. error amplifier the internal error amplifier (ea) regulates the output voltage of the bias supply. it compares a scaled output voltage signal to an internal 2.5 v reference (v ref ) connected to its non?inverting input. the scaled signal is fed into the feedback pin ( v fb ) which is the inverting input of the error amplifier. the output of the error amplifier is available for frequency compensation and connection to the pwm comparator through the comp pin. to insure normal operation, the ea compensation should be selected such that the ea frequency response crosses 0 db below 80 khz. the error amplifier input bias current is less than 1 a over the operating range. the output source and sink currents are typically 110 a and 550 a, respectively. under load transient conditions, comp may need to move from the bottom to the top of the c t ramp. a large current is required to complete the comp swing if small resistors or large capacitors are used to implement the compensation network. in which case, the comp swing will
ncp1030, ncp1031 http://onsemi.com 14 be limited by the ea sink current, typically 110 a. optimum transient response is obtained if the compensation components allow comp to swing across its operating range in 1 cycle. line under and overvoltage detector the ncp103x incorporates individual line undervoltage (uv) and overvoltage (ov) shutdown circuits. the uv and ov thresholds are 2.5 v. a fault is present if the uv is below 2.5 v or if the ov voltage is above 2.5 v. the uv/ov detectors incorporate 175 mv hysteresis to prevent noise from triggering the shutdown circuits. the uv/ov circuits can be biased using an external resistor divider from the input line as shown in figure 34. the uv/ov pins should be bypassed using a capacitor to prevent triggering the uv or ov circuits during normal switching operation. figure 34. uv/ov resistor divider from the input line r 1 r 2 r 3 v in v uv ? + v ov ? + the resistor divider must be sized to enable the controller once v in is within the required operating range. while a uv or ov fault is present, switching is not allowed and the comp pin is effectively grounded. either of these comparators can be used for a different function if uv or ov functions are not needed. for example, the uv/ov detectors can be used to implement an enable or disable function. if positive logic is used, the enable signal is applied to the uv pin while the ov pin is grounded. if negative logic is used, the disable signal is applied to the ov pin while biasing the uv pin from v cc using a resistor divider. oscillator the oscillator is optimized for operation up to 1 mhz and its frequency is set by the external timing capacitor (c t ) connected to the c t pin. the oscillator has two modes of operation, free running and synchronized (sync). while in free running mode, an internal current source sequentially charges and discharges c t generating a voltage ramp between 3.0 v and 3.5 v. under normal operating conditions, the charge (i ct(c) ) and discharge (i ct(d) ) currents are typically 215 a and 645 a, respectively. the charge:discharge current ratio of 1:3 discharges c t in 25 % of the total period. the power switch is disabled while c t is discharging, guaranteeing a maximum duty cycle of 75 % as shown in figure 35. 25 % max duty cycle comp 75% figure 35. maximum duty cycle vs comp c t ramp power switch enabled c t charge signal figure 18 shows the relationship between the operating frequency and c t . if an uv fault is present, both i ct(c) and i ct(d) are reduced by a factor of 7, thus reducing the operating frequency by the same factor. the oscillator can be synchronized to a higher frequency by capacitively coupling a synchronization pulse into the c t pin. in sync mode, the voltage on the c t pin needs to be driven above 3.5 v to trigger the internal comparator and complete the c t charging period. however, pulsing the c t pin before it reaches 3.5 v will reduce the p?p amplitude of the c t ramp as shown in figure 36. figure 36. external frequency synchronization waveforms 3.0 v 3.5 v sync pulse 3.0 v/3.5 v comparator reset free running mode sync mode t1 (f1) t2 (f2) t2 (f2) c t ramp c t voltage range in sync the oscillator frequency should be set no more that 25% below the target sync frequency to maintain an adequate voltage range and provide good noise immunity. a possible circuit to synchronize the oscillator is shown in figure 37. 2 5 v c1 r1 r2 figure 37. external frequency synchronization circuit. c t c t
ncp1030, ncp1031 http://onsemi.com 15 pwm comparator and latch the pulse width modulator (pwm) comparator compares the error amplifier output (comp) to the c t ramp and generates a proportional duty cycle. the power switch is enabled while the c t ramp is below comp as shown in figure 35. once the c t ramp reaches comp, the power switch is disabled. if comp is at the bottom of the c t ramp, the converter operates at minimum duty cycle. while comp increases, the duty cycle increases, until comp reaches the peak of the c t ramp, at which point the controller operates at maximum duty cycle. the c t charge signal is filtered through a one shot pulse generator to set the pwm latch and enable switching at the beginning of each period. switching is allowed while the c t ramp is below comp and a current limit fault is not present. the pwm latch and comparator propagation delay is typically 150 ns. if the system is designed to operate with a minimum on time less than 150 ns, the converter will skip pulses. skipping pulses is usually not a problem, unless operating at a frequency close to the audible range. skipping pulses is more likely when operating at high frequencies during high line and minimum load condition. a series resistor is included for esd protection between the ea output and the comp pin. under normal operation, a 220 mv offset is observed between the c t ramp and the comp crossing points. this is not a problem as the series resistor does not interact with the error amplifier transfer function. current limit comparator and power switch circuit the ncp103x monolithically integrates a 200 v power switch circuit with control logic circuitry. the power switch circuit is designed to directly drive the converter transformer. the characteristics of the power switch circuit are well known. therefore, the gate drive is tailored to control switching transitions and help limit electromagnetic interference (emi). the power switch circuit is capable of switching 200 v. the power switch circuit incorporates sensefet ? technology to monitor the drain current. a sense voltage is generated by driving a sense element, r sense , with a current proportional to the drain current. the sense voltage is compared to an internal reference voltage on the non?inverting input of the current limit comparator. if the sense voltage exceeds the reference level, the comparator resets the pwm latch and switching is terminated. the ncp1030 and ncp1031 drain current limit thresholds are 0.5 a and 1.0 a, respectively. each time the power switch circuit turns on, a narrow voltage spike appears across r sense . the spike is due to the power switch circuit gate to source capacitance, transformer interwinding capacitance, and output rectifier recovery time. this spike can cause a premature reset of the pwm latch. a proprietary active leading edge blanking (leb) circuit masks the current signal to prevent the voltage spike from resetting the pwm latch. the active leb masks the current signal until the power switch turn on transition is complete. the adaptive leb period provides better current limit control compared to a fixed blanking period. the current limit propagation delay time is typically 100 ns. this time is measured from when an overcurrent fault appears at the power switch circuit drain, to the start of the turn?off transition. propagation delay must be factored in the transformer design to avoid transformer saturation. thermal shutdown internal thermal shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction temperature is exceeded. when activated, typically at 150 c, the power switch circuit is disabled. once the junction temperature falls below 105 c, the ncp103x is allowed to resume normal operation. this feature is provided to prevent catastrophic failures from accidental device overheating. it is not intended to be used as a substitute for proper heatsinking. application considerations a 2 w bias supply for a 48 v telecom system was designed using the ncp1030. the bias supply generates an isolated 12 v output. the circuit schematic is shown in figure 38. application note and8119/d describes the design of the bias supply. figure 38. 2 w isolated bias supply schematic gnd comp + 35?76v ? vcc vdrain uv ov ct vfb + ? 22 mbra160t3 mbra160t3 2.2 1m 10 4k99 1k30 10k 0.033 680p 680p 0.01 0.01 2.2 2.2 1:2.78 45k3 34k 12v ncp1030 0.022 100 p mura110t3 499
ncp1030, ncp1031 http://onsemi.com 16 package dimensions micro8 dm suffix case 846a?02 issue f s b m 0.08 (0.003) a s t dim min max min max inches millimeters a 2.90 3.10 0.114 0.122 b 2.90 3.10 0.114 0.122 c --- 1.10 --- 0.043 d 0.25 0.40 0.010 0.016 g 0.65 bsc 0.026 bsc h 0.05 0.15 0.002 0.006 j 0.13 0.23 0.005 0.009 k 4.75 5.05 0.187 0.199 l 0.40 0.70 0.016 0.028 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. 846a?01 obsolete, new standard 846a?02. ?b? ?a? d k g pin 1 id 8 pl 0.038 (0.0015) ?t? seating plane c h j l ? 8x 8x 6x mm inches scale 8:1 1.04 0.041 0.38 0.015 5.28 0.208 4.24 0.167 3.20 0.126 0.65 0.0256 soldering footprint
ncp1030, ncp1031 http://onsemi.com 17 package dimensions so?8 d suffix case 751?07 issue ac seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 soldering footprint
ncp1030, ncp1031 http://onsemi.com 18 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 ncp1030/d micro8 is a trademark of international rectifier. sensefet is a trademark of semiconductor components industries, llc. the products described herein (ncp1030 and ncp1031) may be covered by one or more of the following u.s. patents: 5,418,410; 5,4 77,175. there may be other patents pending. literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

▲Up To Search▲

Price & Availability of NCP1031DR2

	To Download NCP1031DR2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .